• VEST Specification
• VEST Authenticated Encryption Specification
• VEST Hardware Performance Survey
• 20 Gigabit per second VEST performance in 130ηm ASIC

(La traduction en Français de cette page est actuellement en cours de réalisation.)

VEST Hardware-Dedicated Stream Ciphers

Sean O'Neil, Benjamin Gittins and Howard A. Landman

Abstract: VEST ciphers are based on bijective non-linear parallel feedback shift registers assisted by non-linear Residue Number System (RNS) based counters. Four VEST cipher family trees are introduced: 80-bit secure VEST-4, 128-bit secure VEST-8, 160-bit secure VEST-16 and 256-bit secure VEST-32. VEST ciphers return 4 to 32 bits of output per clock cycle while occupying ~5K to ~22K ASIC gates including the finite state machine logic overhead. All VEST ciphers support family keying, variable key sizes and instant re-keying. VEST ciphers are designed exploiting all the advantages of ASIC and FPGA hardware offering high-speed encryption with very low latency and substantial performance improvements comparing with general-purpose or software ciphers implemented in the same area.

Keywords: secret-key cryptography / stream ciphers, hash functions, authenticated encryption, message digest, MAC, message authentication code, fastest hardware cipher, NLFSR, parallel feedback, RNS, residue number system

Available formats: PDF | BibTeX Citation | Reference C code

Authenticated Encryption Mode of VEST Ciphers

Sean O'Neil and Benjamin Gittins

Abstract: This paper demonstrates operation of the authenticated encryption mode in VEST ciphers. All VEST ciphers operating in the authenticated encryption mode with infinite error propagation provide keyed message authentication at the same speed as their keystream generation, with negligible overhead and maintaining their security ratings.

Keywords: secret-key cryptography / stream ciphers, hash functions, authenticated encryption, message digest, MAC, message authentication code, fastest hardware cipher, NLFSR, parallel feedback, RNS, residue number system

Available formats: PDF | BibTeX Citation | Reference C code

VEST-32, 256-bit secure, Single-Pass Authenticated Encryption. 20 Gigabit/s @ 312MHz on 110ηm LSI Logic RapidChip Platform ASIC Technology <45K Gates, Zero SRAM and <150mW

Benjamin Gittins

Abstract: a preliminary report on the static-timing, R-Cell, die-area and static- power requirements of the complete data-path of VEST-32 ciphers on LSI Logic RapidChip 180ηm and 110ηm Technologies. Based on the conservative standard RapidChip design front-end sign-off process, VEST-32 can effortlessly satisfy a demand for 256-bit secure 10 Gb/s authenticated encryption @ 167 MHz on 180ηm LSI Logic RapidChip platform ASIC technologies in less than 45K Gates and zero SRAM. On the 110ηm Rapidchip technologies, VEST-32 offers 20 Gb/s authenticated encryption @ 320 MHz in less than 45 K gates. Similar bandwidth performance may be achievable with reduced circuit area using a custom sign-off process.